Design-Reuse

Renesas Technology Develops Technique that Overcomes Effects of Threshold Variation to Stabilize the Operation of Embedded SRAM built with 65nm Process

High yield achieved for the world's smallest level 6-transistor SRAM memory-cell area (0.494µm 2) ; stabilization technique addresses variability of transistor characteristics. Tokyo, June 15, 2006 −− ...
Electronic Design

Should Dual Rail Go Mainstream in Deep Nanometer Era?

Deep sub-nanometer designs are stressed with large process variability. SRAM-bits have the most aggressive design rules in the SoCs, and the most variability. A dual rail solution offsets some of the ...
Design-Reuse

Embedded SRAM test and repair moves on-chip

SAN MATEO, Calif. — With the rollout of its Star Memory System, an on-chip test and repair mechanism for embedded SRAM, memory compiler specialist Virage Logic Corp. is making good on its promise to ...