Vasu Raj Jain Wins 2026 Global Recognition Award for Transforming Large-Scale SaaS Infrastructure

Vasu Raj Jain engineered a scalable multi-tenant SaaS platform, reducing onboarding from 52 to 2 days, eliminating deployment ...
IEEE

Compact Modeling of Process Variation and Reliability Predictions for Nanosheet Gate-All-Around FET

Abstract: In this work, a semi-analytical compact model is developed to quantify the impact of random process variations on nanosheet field-effect transistors (NSFETs) at the 3nm technology node.
IEEE

Meta-Optimized LDMOS Process–Device Co-Optimization: Extrapolation-Enhanced Modeling With Wafer-Level Validation

Abstract: Accurate and efficient modeling of lateral double-diffused MOS (LDMOS) devices is critical for process optimization and reliability analysis, especially under limited simulation budgets.