New Electronics

Microchip releases C++ synthesis suite for PolarFire FPGA algorithm development

Microchip Technology has added an HLS design workflow, called SmartHLS, to its PolarFire FPGA families to allow C++ algorithms to be directly translated to FPGA-optimised Register Transfer Level (RTL) ...
EDN

Tool develops FPGA algorithms from C/C++

CoDeveloper FPGA design tool allows algorithms to be developed and debugged with existing C/C++ tools. The tool helps identify dataflow bottlenecks, generates debugging visualizations for ...
EDN

Implement a simple digital-serial NRZ data-recovery algorithm in an FPGA

Serial-data links embed clocks in their data streams, and those clocks must be recovered at the receiver end. This Design Idea describes a data/clock-recovery algorithm for an NRZ (non-return-to-zero) ...
Nature

Hardware Architecture for Cryptographic Algorithms on FPGA

Field Programmable Gate Arrays (FPGAs) have emerged as a versatile platform for implementing cryptographic algorithms, offering a balance between flexibility, performance and energy efficiency. Recent ...
Nature

High-Performance Sorting Algorithms and Architectures Using FPGA

Field-programmable gate arrays (FPGAs) offer a unique platform for the implementation of high-performance sorting algorithms by combining inherent parallelism with customisable hardware architectures.
The Next Platform

Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Learning?

Continued exponential growth of digital data of images, videos, and speech from sources such as social media and the internet-of-things is driving the need for analytics to make that data ...