IEEE

Design and Analysis of 8× 8 SRAM Memory Array using 45 nm Technology at 100 MHz

Abstract: The main goal of this paper is to build an 8 by 8-bit SRAM memory array using 45nm CMOS technology. The SRAM array is read by a 3-bit address using a 3-to-8 decoder. The SRAM cells are made ...
IEEE

Design Automation of Analog and Mixed-Signal Circuits Using Neural Networks—A Tutorial Brief

Abstract: This tutorial brief shows how Artificial Neural Networks (ANNs) can be used for the optimization and automated design of analog and mixed-signal circuits. A survey of conventional and ...