Electronic Design

Design-For-Test The Smart Way: dFT With A "Big T" And A "Little d"

Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding ...
Electronic Design

What’s Next for Physically Aware DFT?

Why isolated flows negatively impact design schedule and PPA. Benefits of unified DFT, synthesis, and physical design flows. Physical implementation optimization methods for test compression and scan ...
EDN

ITC tutorials span DFT basics to RF test

The 2006 International Test Conference is scheduled for the week of October 22 in Santa Clara, CA. For more on this year’s ITC, read our interview with program chair Anne Gattiker. Semiconductor test ...
Semiconductor Engineering

Making IC Test Faster And More Accessible: Part 1

The fundamental challenges of IC test have been the same for a long time. At the heart of all test strategies is controllability and observability. First, control the state of the chip with known test ...
Semiconductor Engineering

Enabling Test Strategies For 2.5D, 3D Stacked ICs

Improved testability, coupled with more tests at more insertion points, are emerging as key strategies for creating reliable, heterogeneous 2.5D and 3D designs with sufficient yield. “With chiplets, ...