IEEE

Comprehensive Review of Low-Power VLSI Design Techniques: Challenges, Cryptographic Implementations, and Future Prospects

Abstract: The increasing demand for secure and energy-efficient computing has made low-power cryptographic hardware a crucial aspect of modern VLSI design. Achieving an optimal balance between power ...
IEEE

A Review on Logic Gate Design and Layout Optimization in Cadence Virtuoso for Low-Power VLSI Applications

Abstract: This paper reviews logic gate design and layout optimization for low-power VLSI circuits using Cadence Virtuoso. Conventional CMOS, GDI, and MGDI logic styles are compared in terms of power, ...