IEEE

Modeling, Analysis, and Comparison of Voltage and Charge Sampling Techniques in Sub-Sampling PLL Design

Abstract: This paper compares two different architectures for implementing a sub-sampling phase-locked loop (SS-PLL). First, a time-domain model is used to analyze the noise contributions of the ...
Nature

Sub-angstrom accuracy in protein loop reconstruction by robotics-inspired conformational sampling

You have full access to this article via your institution. Figure 2: Performance of the KIC loop reconstruction protocol. The described state-of-the-art loop ...
IEEE

A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS

Abstract: A 60 GHz sub-sampling PLL implemented in 40 nm CMOS is presented in this paper. The sub-sampling phase detector (SSPD) runs at 30 GHz after an inductively-peaked static divide-by-two. Thanks ...