GitHub

This project implements a 4-bit Unsigned Parallel Multiplier in Verilog

📌 Overview Unlike a serial multiplier, a parallel multiplier generates all partial products simultaneously and adds them using combinational adders to produce the final result in a single clock cycle ...
IEEE

FPGA Implementation of an Efficient Hybrid Multiplier: A VLSI Architecture Utilizing Hybrid Adder Technology

Abstract: The evolution of Digital Signal Processing (DSP) systems and embedded systems within the VLSI era has significantly impacted computational speed, chip size, and power consumption, ...
IEEE

Energy-Efficient Posit Multiplier Architecture for Precision-Centric Quantum Image Processing on Vlsi Platforms

Abstract: This work introduces a novel method for boosting the efficiency of digital image processing platforms through the design and simulation of modular multiplier architectures based on Posit ...