IEEE

Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Abstract: The increasing popularity of large language models (LLMs) has paved the way for their application in diverse domains. This paper proposes a benchmarking framework tailored specifically for ...
IEEE

Detecting Unknown Hardware Trojans in Register Transfer Level Leveraging Verilog Conditional Branching Features

Abstract: Hardware Trojans have concealed modifications to integrated circuits (ICs) that can alter their functions, performance, or security properties. Existing Trojan detection methods are designed ...
GitHub

Single-Cycle MIPS Processor on Cyclone V (5CSEMA5)

This project implements a single-cycle MIPS-style processor in Verilog and deploys it on the Cyclone V FPGA (DE1-SoC, 5CSEMA5). The design includes a fully integrated datapath and control unit capable ...
GitHub

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation

benchmark folder contains 3 kinds of design, arithmetic circuit, digital circuit, and advanced circuit repectively. Each design class folder several designs, and each design contains 3 level design ...