The shift to multi-die assemblies is forcing changes in how chips are tested and inspected in order to achieve sufficient yield ramp or respond more quickly to yield excursions.

GRENOBLE, France--(BUSINESS WIRE)--Hprobe, a provider of turnkey semiconductor Automatic Test Equipment (ATE) for magnetic devices, today announced a breakthrough magnetic test head revolutionizing ...

In the fast-paced world of semiconductor manufacturing, achieving higher yields and reducing costs are constant challenges. Ideally, yield should only be impacted by unavoidable defects when ...

Test-flow partitioning between wafer sort and final package test can have a dramatic impact on the cost of test. In some cases, the migration of package tests can be done over time, but the test ...

The back-end semiconductor manufacturing process refers to the IC packaging and testing that people often hear about. Specifically, the process known as chip probing (CP) is conducted to test the ...

Motorola Inc.’s semiconductor products sector (SPS) today said it has developed and qualified the first wafer level burn-in and test (WLBT) process for flip-chip microprocessors. Motorola aims to ...

The new facility forms part of ICsense’s latest strategic investment programme and is intended to support growing demand for custom ASIC solutions across multiple industries. The global ASIC market is ...

The emergence of 3-D ICs presents test challenges that extend from design-for-test tools from design-automation companies to device handlers from equipment firms including Advantest and Multitest. A ...

May 19, 2011, 4:17 PM EDT / Source: GlobeNewswire FREMONT, Calif., May 19, 2011 (GLOBE NEWSWIRE) -- Aehr Test Systems (Nasdaq:AEHR), a worldwide supplier of semiconductor test and burn-in equipment, ...

Rapidus on Friday announced that it had begun prototyping of test wafers with 2nm gate-all-around (GAA) transistor structures at its IIM-1 facility in Japan. The company confirmed that early test ...