EDN

Synthesizable DSP cores are optimized for multimedia

Austin, Tex. — StarCore's new SC2200 and SC2400 synthesizable digital signal processor cores are optimized for multimedia, communications, and consumer applications. The cores are based on the ...
Design-Reuse

Synopsys Enhances DesignWare Synthesizable IP for AMBA 2 and AMBA 3 AXI Protocols

MOUNTAIN VIEW, Calif. -- April 25, 2007-- Synopsys, Inc. (Nasdaq: SNPS - News), a world leader in semiconductor design software, today announced the 2007.04a release of DesignWare® synthesizable ...
EDN

Synthesizable analog IP key to embedded SoC platforms

Perhaps, the most compelling new trend in system-level embedded design is the concept of application “platforms”. Essentially, platforms are intended to make the development of complex, ...
Design-Reuse

Synthesizable verification IP speeds design cycle

Today's deep sub-micron process technology allows the creation of an incredible range of System on Chip (SoC)-based electronic products. These products, however, are sources of methodology and ...
Semiconductor Engineering

Ensure Equivalence Of Synthesizable C++/SystemC Designs Against Generated/Handwritten RTL

High-level synthesis (HLS) is a design flow in which design intent is described at a higher level of abstraction than RTL, such as in SystemC/C++ or MATLAB. HLS tools are expected to synthesize this ...
Semiconductor Engineering

Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs (Kyungpook National University)

“Clock tree synthesis (CTS) is an important process in determining overall chip timing and power consumption. The CTS is also a time-consuming process for checking the clock tree. If the chip design ...
CIOL

Synopsys fully synthesizable PowerPC cores

MOUNTAIN VIEW, USA: Synopsys Inc. has announced the availability of fully synthesizable implementations of the IBM PowerPC 460 and cache configurable PowerPC 405 embedded microprocessor cores as ...