EDN

Static timing analysis taken to RT level

San Mateo, Calif. – InTime Software Inc. will unveil a register-transfer-level timing tool this week intended to help IC designers develop timing-accurate RTL code before they move to synthesis, ...
Electronic Design

FPGA Tool Suite Adds Native Static Timing Analysis

With so many ASIC designers moving over to FPGAs for implementation, FPGA tool flows are looking more and more like ASIC flows. Case in point: Actel's Libero IDE 6.2 adds native static timing analysis ...
Semiconductor Engineering

The Demise Of Static Timing Verification?

The chip industry traditionally has relied on margins to help them mitigate timing problems, but an increasing array of factors are now influencing timing. Can static timing analysis evolve to address ...
Business Wire

Cadence Announces Tempus Power Integrity Solution for Signoff Timing-Aware IR Drop Analysis

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the Tempus ™ Power Integrity Solution, the industry’s first comprehensive static timing/signal integrity ...
Embedded

Static timing analysis: bridging the gap between simulation and silicon

Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is ...
Semiconductor Engineering

What Happened To Statistical Static Timing Analysis?

About five years ago if you listened to the marketing messages in the EDA industry, you would have thought it would be impossible to produce chips without statistical static timing analysis (SSTA).