The company appears well positioned to challenge CPU incumbents with high performance RISC-V CPUs and Vector Extensions to the open ISA architecture. The RISC-V CPU Instruction Set Architecture (ISA) ...
Benchmarking tool Geekbench has been updated to version 6.4, seeing added support for RISC-V Vector Extensions and Arm Scalable Matrix Extensions. Geekbench is a highly-used benchmark tool, providing ...
The computing industry has reached a significant milestone with the ratification of the 1.0 RISC-V Vector Specification. This development marks the beginning of a new era in computing efficiency, as ...
SAN MATEO, Calif.--(BUSINESS WIRE)--SiFive Inc., the founder and leader of RISC-V computing, today announced the release of the latest version of its SiFive® Intelligence™ X280 processor, which ...
A new technical paper titled “Test-driving RISC-V Vector hardware for HPC” was published by researchers at University of Edinburgh. “Whilst the RISC-V Vector extension (RVV) has been ratified, at the ...
Join our daily and weekly newsletters for the latest updates and exclusive content on industry-leading AI coverage. Learn More SiFive, a processor design company pursuing the open hardware model of ...
San Jose, CA, Nov. 06, 2020 (GLOBE NEWSWIRE) -- Andes Technology Corporation (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and founding Premier member ...
A technical paper titled “Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications” was published by researchers at Barcelona Supercomputing Center ...
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