TechRepublic

Design and Testing of Prefix Adder for High Speed Application by Using Verilog HDL

Parallel prefix adder is the most flexible and widely used for binary addition. Parallel prefix adders are best suited for VLSI implementation. Numbers of parallel prefix adder structures have been ...
TechRepublic

Design and Characterization of Fault Tolerant Power Parallel Prefix Adders Using FPGA Design

Parallel-prefix adders (also known as carry tree adders) are known to have the best performance in VLSI designs. However, this performance advantage does not translate directly into FPGA ...
mccormick.northwestern.edu

COMP_ENG 368, 468: Programming Massively Parallel Processors with CUDA

A hands-on introduction to parallel programming and optimizations for 1000+ core GPU processors, their architecture, the CUDA programming model, and performance analysis. Students implement various ...
mccormick.northwestern.edu

COMP_SCI 368, 468: Programming Massively Parallel Processors with CUDA

This course focuses on developing and optimizing applications software on massively parallel graphics processing units (GPUs). Such processing units routinely come with hundreds to thousands of cores ...