Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Design-Reuse

Automatic C-to-VHDL testbench generation shortens FPGA development time

Verifying behavior early and often has become critical with FPGAs. Newer generations of FPGAs have gate counts that rival the largest custom ASICs of five years ago. This fact, coupled with the broad ...
Design-Reuse

QuickLogic Announces Orders for Strategic Radiation Hardened FPGA Development Kit

SAN JOSE, Calif., Jan. 14, 2026 -- QuickLogic Corporation, a developer of embedded FPGA (eFPGA) Hard IP, Strategic Radiation Hardened, Antifuse and ruggedized FPGAs, announced today that it has ...
CU Boulder News & Events

ECEA 5361 Hardware Description Languages for FPGA Design

This course will give you the foundation for using Hardware Description Languages, specifically VHDL and Verilog for Logic Design. You will learn the history of both VHDL and Verilog and how to use ...
EDN

A SystemC/TLM based methodology for IP development and FPGA prototyping

With the advent of System-on-Chip technology, designs are becoming bigger in size and thus highly complex, time-to-market is becoming critical, and at the same time, RTL methodologies are generally ...