In the first part of this series on the proposed Cache Coherence Interconnect for Accelerators (CCIX) standard, we talked about the issues of cache coherence and the need to share memory across ...

If multiple devices, such as the CPU and peripherals, access the same cacheable memory region, cache and memory can become incoherent. This is illustrated in Figure 7. Suppose the CPU accesses a ...

Scaling processing performance beyond the frequency and power envelope of single core systems has led to the emergence of multi-core clusters. Data access management within such processing systems ...

In a modern, multicore chip, every core -- or processor -- has its own small memory cache, where it stores frequently used data. But the chip also has a larger, shared cache, which all the cores can ...

Part 1: A look at the impact of communication across multiple processors on an SoC and how to to make that more efficient. Managing how the processors in an SoC talk to one another is no small feat, ...

In addition to the cache-coherence protocol discussed here, Sun already used formal verification successfully to verify other protocol-related problems. Architecture-level protocol verification is a ...