For decades, process and design scaling has triggered the adoption of transformative test solutions. About twenty years ago, when at-speed test became a de-facto requirement, on-chip compression ...
When a global provider of air traffic, navigation, and landing system solutions began implementing its next-generation system, limitations of an existing test and debug methodology directly impacted ...
IC designers now have a powerful weapon in the struggle against rising test costs: commercially available EDA solutions that provide fast and effective means to implement scan compression on-chip. By ...
The fundamental challenges of IC test have been the same for a long time. At the heart of all test strategies is controllability and observability. First, control the state of the chip with known test ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results