The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. To ...

Yield improvement at sub 100-nm technologies relies on the latest scan test techniques. As IC feature sizes shrink below 90 nm, in-line inspection techniques to determine yield-limiting problems ...

As design size and complexity increase, so too does the cost of test. Both the design community and the test industry are looking at various approaches to lower the cost of manufacturing test. This ...

As chips become more heterogeneous with more integrated functionality, testing them presents increasing challenges — particularly for high-speed system-on-chip (SoC) designs with limited test pin ...

Boundary scan is well established in the industry, a fact strengthened by major ATE companies like Agilent Technologies and Teradyne that have added boundary scan capabilities to their in-circuit ...